1. Field of the Invention
The present invention relates generally to the design of electronic systems. In particular, the present invention is a method and circuit for shortening the design cycle of integrated circuits.
2. Description of the Prior art
The design of VLSI and other integrated circuits is typically done using computer-aided design (CAD) work stations. Information stored in the work station includes cell libraries (data representative of the interconnections between transistors to form basic circuit logic elements or macros including AND, OR and other logic gates, adders, counters, flip flops, memory, registers, etc.), placement programs for efficiently arranging the macros on an integrated circuit substrate, router programs for laying out the interconnections between the macros, simulation programs and other software design tools. Knowing the required specifications of the integrated circuit, the designer has traditionally followed design procedures of the type illustrated in FIG. 1.
The main logic function of the integrated circuit is first schematically defined in terms of the component macros from which it is to be formed and a series of net lists which characterize terminals of the macros which are to be interconnected. Once the integrated circuit has been initially laid out in this manner, the design must be thoroughly tested to ensure its proper operation. Integrated circuit testing is typically performed in two sequential phases. The first phase involves functional testing or logic and timing simulations. The second phase involves testability analysis.
Logic and timing simulations are performed to determine whether the integrated circuit is functioning properly, i.e. whether the logic is operating in the intended manner. These simulations typically require one to five days of the designer's time. Errors in the design will undoubtedly be identified during logic and timing simulation. Logic changes necessitated by these errors often take about one day of the designer's time. Modification (redefinition) of the integrated circuit's schematic as a result of the logic changes takes another one to two days of the designer's time. Three to eight days are therefore required for each iteration of the logic and timing simulation phase. Furthermore, with larger VLSI integrated circuits it is often necessary to repeat these operations eight to fifteen times before all of the logic and timing problems have been worked out. It is not uncommon for a designer to devote two to three months to an integrated circuit design before it is functionally complete.
VLSI circuit chips must also be capable of being thoroughly tested following their manufacture. The design is therefore subjected to a testability analysis to ensure that it has this capability. A number of circuit test techniques such as built-in self-test and scan design are known and implemented in the design to facilitate this objective. Testing an integrated circuit involves viewing the circuit as an array of flip flops separated from one another by combinational logic. A set of test operands is clocked through the chip and their resultant outputs analyzed to determine whether or not the macros are functioning properly. In the case of integrated circuits with built-in self-test circuitry the test operands are random when initially applied to the main logic function, but become increasingly less random due to the combinational logic. The result is that circuits deep within the integrated circuit may not be adequately exercised. In order to find out the level of testability coverage for the circuit, the design is subjected to testability analysis.
The testability analysis involves two distinct aspects. The first is initialization. The second is the actual testability evaluation. During this step the testability analyzer calculates the controllability and observability values which are then compounded to determine the final coverage number. The integrated circuit must be capable of being initialized before it is tested, and for this purpose generally includes an input terminal for receiving Master Clear signals. The Master Clear signal comes into the chip through a regular signal pin. In the built-in self-test circuit environment the Master Clear pin, as all the other signal pins, is by definition connected to one bit of the test register. A circuit is initialized when all of its memory-type macros (e.g. non-combinational macros) such as flip flops, RAM's, counters, etc. are in a known state. Generally, this imposes the following conditions on the designer:
1. For memory-type macros which have a Clear or Set input, that input must be made active or set to a first or logic one state, if it is a true input, or a second or logic zero state, if it is an inverted input, during the initialization sequence;
2. For memory-type macros which do not have a Clear or Set input, but have an Enable input, the Enable input has to be active or set to a first or logic one state, if it is a true input, or a second or logic zero state, if it is an inverted input, to enable the passage of initialization data; and
3. For memory-type or multiplexer-type macros which do not have any of the above inputs, but have a Select input, it must be verified that no feedback paths are selected during initialization.
To be thoroughly testable the integrated circuit must be both controllable and observable. A circuit is controllable if the inputs and outputs of its component logic macros can be changed by signals applied to the input pins of the circuit. A circuit is observable if changes to the inputs and outputs of its component logic macros generate corresponding changes at the circuit output pins. If the integrated circuit is to be controllable and observable during the test procedures, data must be capable of freely flowing through the circuit. The following conditions must therefore be met during the test:
1. Enable inputs of logic macros must be active;
2. Clear inputs must be disabled to permit the propagation of simulation data through the circuit;
3. Select inputs must be at logic zero and logic one states equal amounts of time to select all the input data presented to the inputs of multiplexers; and
4. All macro outputs must be connected forward.
As illustrated in FIG. 1, the testability analysis is usually performed following the definition and simulation of the integrated circuit logic. The testability analysis itself often requires one to four days. Logic changes and associated schematic modifications (redefinitions) necesSitated by the testability analysis can each take another day to perform. Logic and timing simulations for the modified overall circuit, often requiring from one to five days of the designer's time, must then be repeated. Each iteration of the testability analysis requires four to eleven days. It is not uncommon to repeat this sequence of operations six to ten times before the testability analysis and associated design changes are completed. Four to six months are therefore required to complete both the logic simulation and testability analysis for a VLSI circuit.
The classic design approach described above has other drawbacks. Chip level initialization is often solved by adding on the normal Master Clear line a circuit which produces an n-clock long pulse at the start of the test sequence. The value of n is determined by the particular design requirements. This circuit has to be switched off after the desired number of clocks, and must be more or less custom-made for each design. Testability analysis problems are sometimes overcome by adding special circuits to the flip flop inputs to (mostly) enable their normal operation during test. Both of these solutions are done on an ad hoc basis, and require valuable space on the integrated circuit.
It is evident that there is a continuing need for improved circuit design techniques. A methodology and circuit which reduce the time required for the testability analysis and the functional simulation generated by the testability changes is needed. The improved procedures should be capable of implementation on a CAD work station. Circuitry added to the chip to facilitate these objectives should occupy as little space as necessary.